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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 21560 rev: a amendment/ +1 issue date: april 1998 am79761 physical layer 10-bit transceiver for gigabit ethernet (gigaphy-sd) distinctive characteristics n gigabit ethernet transceiver operates at 1.25 gigabits per second (gbps) n suitable for both coaxial and optical link applications n 10-bit ttl interface for transmit and receive data n monolithic clock synthesis and clock recovery requires no external components n word synchronization function (comma detect) n low power operation - 700 mw typical n 64-pin standard pqfp 14 x 14 mm (0? c - 70? c) 10 x 10 mm (0? c - 50? c) n 125 mhz ttl reference clock n loopback diagnostic n single +3.3 v supply general description the am79761 gigabit ethernet physical layer serial- izer/deserializer (gigaphy-sd) device is a 1.25 gbps ethernet transceiver optimized for gigabit ethernet/ 1000base-x applications. it implements the physical medium attachment (pma) layer for a single port. the gigaphy-sd device can interface to ?er-optic media to support 1000base-lx and 1000base-sx applications and can interface to copper coax to sup- port 1000base-cx applications. the functions performed by the device include serializ- ing the 8b/10b 10-bit data for transmission, deserializ- ing received code groups, recovering the clock from the incoming data stream, and word synchronization. when transmitting, the gigaphy-sd device receives 10-bit 8b/10b code groups at 125 million code groups per second. it then serializes the parallel data stream, adding a reference clock, and transmits it through the pecl drivers. when receiving, the gigaphy-sd device receives the pecl data stream from the network. it then recovers the clock from the data stream, deserializes the data stream into a 10-bit code group, and transmits it to the physical coding sublayer (pcs) logic above. option- ally, it detects comma characters used to align the in- coming word.
2 am79761 preliminary block diagram d q q d serial to parallel parallel to serial rx+ rx- frame logic 10 tx+ tx- ewrap rxd[0:9] rclk rclkn com_det en_cdet txd[0:9] refclk pll clock multiply 10 10 20 clock recovery comma detect 21560a-1
am79761 3 preliminary connection diagram logic symbol 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dvss txd0 txd1 txd2 dvdd txd3 txd4 txd5 txd6 dvdd txd7 txd8 txd9 dvss dvss n/c n/c com_det dvss_t rxd0 rxd1 rxd2 dvdd_t rxd3 rxd4 rxd5 rxd6 dvdd_t rxd7 rxd8 rxd9 dvss_t n/c test1 ewrap test2 dvss refclk test3 en_cdet dvss test4 n/c dvdd dvdd_t rclkn rclk dvss_t n/c dvdd_p tx+ tx- dvdd_p dvdd avss avdd dvss dvdd rx+ dvdd_p rx- dvss dvdd n/c 21560a-2 note: n/c = no connect am79761 gigaphy-sd dvdd dvdd_t dvdd_p avdd dvss dvss_d dvss refclk rclk rclkn en_cdet ewrap com_det test4 tdst [3:1] txd [0:9] rxd [0:9] tx+ tx rx+ rx to pcs transceiver phy control test port 21560a-3
4 am79761 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. device number/description am79761 physical layer 10-bit transceiver for gigabit ethernet gigaphy-sd) package size option -10 = 10 x 10 mm body size -14 = 14 x 14 mm body size temperature range c = commercial (0?c to +70?c) am79761 c y package type y = 64-pin plastic quad flat pack (pdh064) -10 valid combinations am79761yc am79761yc -10 -14
am79761 5 preliminary related products part no. description am7990 local area network controller for ethernet (lance) am7992b serial interface adapter (sia) am7996 ieee 802.3/ethernet/cheapernet transceiver am79c90 cmos local area network controller for ethernet (c-lance) am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex+) am79c871 quad fast ethernet transceiver for 100base-x repeaters (qfexr) am79c981 integrated multiport repeater plus (imr+) am79c982 basic integrated multiport repeater (bimr) am79c983 integrated multiport repeater 2 (imr2) am79c984a enhanced integrated multiport repeater (eimr) am79c985 enhanced integrated multiport repeater plus (eimr+) am79c987 hardware implemented management information base (himib) am79c988a quad integrated ethernet transceiver (quiet) am79c900 integrated local area communications controller (ilacc) am79c940 media access controller for ethernet (mace) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa+ single-chip ethernet controller for isa (with microsoft?plug n play?support) am79c961a pcnet-isa ii full duplex single-chip ethernet controller for isa am79c965 pcnet-32 single-chip 32-bit ethernet controller am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c970a pcnet-pci ii full duplex single-chip ethernet controller (for pci bus) am79c971 pcnet- fast single-chip full-duplex 10/100 mbps ethernet controller for pci local bus
6 am79761 preliminary pin designation listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 dvss 17 n/c 33 dvss_t 49 n/c 2 txd0 18 test1 34 rxd9 50 dvdd 3 txd1 19 ewrap 35 rxd8 51 dvss 4 txd2 20 test2 36 rxd7 52 rx- 5 dvdd 21 dvss 37 dvdd_t 53 dvdd_p 6 txd3 22 refclk 38 rxd6 54 rx+ 7 txd4 23 test3 39 rxd5 55 dvdd 8 txd5 24 en_cdet 40 rxd4 56 dvss 9 txd6 25 dvss 41 rxd3 57 avdd 10 dvdd 26 test4 42 dvdd_t 58 avss 11 txd7 27 n/c 43 rxd2 59 dvdd 12 txd8 28 dvdd 44 rxd1 60 dvdd_p 13 txd9 29 dvdd_t 45 rxd0 61 tx- 14 dvss 30 rclkn 46 dvss_t 62 tx+ 15 dvss 31 rclk 47 com_det 63 dvdd_p 16 n/c 32 dvss_t 48 n/c 64 n/c
am79761 7 preliminary pin description tx+, tx- serial transmit data pecl output these pins are the 1000base-x port differential driv- ers which transmit the serial stream to the network. these pins are connected to the copper or ?er optic connectors. when ewrap is low, the pins assume normal oper- ation. when high, tx+ is logic high and tx- is logic low. rx+, rx- serial receive data pecl input these pins are the 1000base-x port differential re- ceiver pair, receiving a serial stream of data from the network. these pins are connected to the copper or ?er optic connectors. when ewrap is low, the pins assume normal oper- ation. the pins are internally biased. txd[0:9] transmit data ttl input the txd[0:9] pin is a set of 10 data signals which are driven from the physical coding sublayer (pcs) above. the 10 bits of data are clocked in parallel on the rising edge of refclk. txd0 is transmitted ?st on tx . rxd[0:9] receive data ttl output the rxd[0:9] pin is a set of 10 data signals which are sent to the physical coding sublayer (pcs) above. the 10 bits of data are clocked out in parallel on the rising edges of rclk and rclkn. rxd0 is received ?st on rx . refclk reference clock ttl input this input is used for the 125-mhz clock. the rising edge of this clock latches txd[0:9] into an input regis- ter. this clock serves as the reference clock at 1/10th the baud rate for the pll. rclk, rclkn receive clock ttl output these pins provide the differential receive clock sig- nals, derived from the rx data stream, and are at 1/20th the baud rate of the receive stream. parallel data on rxd[0:9] is provided at each rising transition of rclk and rclkn. en_cdet enable comma detect ttl input this pin is used to enable the word synchronization mode. when logic high, the com_det output is en- abled and word synchronization is active. com_det comma detect indicator ttl output comma detect is asserted to indicate that the incoming word on rxd[0:9] contains a comma character (0011111xxx). com_det goes high for half of a rclk period, and can be captured when rckln is rising. in order for com_det to provide indication, en_cdet must be enabled (logic high). ewrap loopback enable ttl input when ewrap is asserted, the transmitted data stream is sent back to the receiver through an internal loop- back path. tx+ is logic high, and tx- is logic low in this mode. this pin is logic low for normal operation. test[1:3] factory test pins input these pins should be tied to dvdd for normal operation. test[4] factory test pin output this pin should be left unconnected for normal operation. dvdd power these pins supply power to the digital blocks of the device. they must be connected to a 3.3 v 5% source. dvdd_t ttl power these pins supply power to the ttl blocks of the de- vice. they must be connected to a 3.3 v 5% source. dvdd_p pecl power these pins supply power to the pecl blocks of the de- vice. they must be connected to a 3.3 v 5% source. it is critical that the signal supplied to these pins are clean to ensure good performance of the device.
8 am79761 preliminary avdd analog power these pins supply power to the analog blocks of the device. they must be connected to a 3m.3 v 5% source and require careful decoupling to ensure proper device performance. dvss ground these pins are the ground connections for the digital blocks. they must be connected to the common external ground plane. dvss_t ground these pins are the ground connections for the ttl blocks. they must be connected to the common exter- nal ground plane. avss ground these pins are the ground connections for the analog blocks. they must be connected to an analog ground plane.
am79761 9 preliminary functional description overview the gigaphy-sd device provides the pma functionality for 1000base-x systems. the gigiaphy-sd communi- cates with the pcs through the 10-bit code groups and communicates with the physical medium dependent (pmd) layer to transmit and receive data from the net- work, through either ?er optic or copper coax media. the gigaphy-sd device consists of the following functional blocks: n 1000base-x transmit block including: clock synthesizer serializer and transmission interface n 1000base-x receive block including: clock recovery deserializer word alignment and synchronization clock synthesizer the am79761 clock synthesizer multiplies the refer- ence frequency provided on the refclk pin by 10 to achieve a baud rate clock at nominally 1.25 ghz. the clock synthesizer contains a fully monolithic pll which does not require any external components. serializer the am79761 device accepts ttl input data as a par- allel 10-bit character on the txd[0:9] bus which is latched into the input latch on the rising edge of refclk. this data will be serialized and transmitted on the tx pecl differential outputs at a baud rate of ten times the frequency of the refclk input, with bit txd0 transmitted ?st. user data should be encoded for transmission using the 8b/10b block code de- scribed in the ieee 802.3 speci?ation. transmission character interface an encoded byte is 10 bits and is referred to as a trans- mission character. the 10-bit interface on the am79761 device corresponds to a transmission char- acter. this mapping is shown in table 20. table 20. transmission order and mapping of an 8b/10b character clock recovery the am79761 device accepts differential high speed serial inputs on the rx pins, extracts the clock and retimes the data. the am79761 clock recovery circuitry is completely monolithic and requires no external com- ponents. for proper operation, the baud rate of the data stream to be recovered should be within 0.01% of ten times the refclk frequency. for example, if the refclk used is 125 mhz, then the incoming serial baud rate must be 1.25 gigabaud 0.01 percent. deserializer the re-timed serial bit stream is converted into a 10-bit parallel output character. the am79761 device provides complementary ttl recovered clocks, rclk and rclkn, which are at 1/20th of the serial baud rate. this architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit half-word in the downstream controller chip. the clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. the serial data is re-timed by the internal high-speed clock and deserialized. the resulting parallel data will be captured by the adjoining protocol logic on the rising edges of rclk and rclkn. in order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of rclk and rclkn. if serial input data is not present or does not meet the required baud rate, the am79761 will continue to pro- duce a recovered clock so that downstream logic may continue to function. the rclk and rclkn output frequency under these circumstances may differ from their expected frequency by no more than 1 percent. parallel data bits t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 8b/10b bit position j h g f i e d c b a comma character x x x 1111100 last data bit transmitted first data bit transmitted
10 am79761 preliminary word alignment the am79761 device provides 7-bit comma character recognition and data word alignment. word synchroni- zation is enabled by asserting en_cdet high. when synchronization is enabled, the am79761 device con- stantly examines the serial data for the presence of the comma character. this pattern is 0011111xxx, where the leading zero corresponds to the ?st bit received. the comma sequence is not contained in any normal 8b/10b coded data character or pair of adjacent char- acters. it occurs only within special characters, known as k28.1, k28.5, and k28.7, which are de?ed speci? cally for synchronization purposes. improper alignment of the comma character is de?ed as any of the follow- ing conditions: 1. the comma is not aligned within the 10-bit trans- mission character such that txd0...txd6 = ?011111. 2. the comma straddles the boundary between two 10-bit transmission characters. 3. the comma is properly aligned but occurs in the re- ceived character presented during the rising edge of rclk rather than rclkn. when en_cdet is high and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned properly in rxd[0:9]. this results in proper character and half-word alignment. when the parallel data alignment changes in response to an improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. however, the synchronization character and subsequent data will be output correctly and properly aligned. when en_cdet is low, the current align- ment of the serial data is maintained inde?itely, regardless of data pattern. when encountering a comma character, com_det is driven high to inform the user that realignment of the parallel data ?ld may have occurred. the com_det pulse is presented simultaneously with the comma char- acter and has a duration equal to the data, or half of an rclk period. the com_det signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of rclkn. functional waveforms for synchronization are given in figure 18 and figure 19. figure 18 shows the case when a comma character is detected and no phase adjustment is necessary. it illus- trates the position of the com_det pulse in relation to the comma character on rxd[0:9]. figure 19 shows the case where k28.5 is detected, but it is out of phase and a change in the output data alignment is required. note that up to three characters prior to the comma character may be corrupted by the realignment process. figure 18. detection of a properly aligned comma character rclk rclkn com_det rxd[0:9] k28.5 tchar tchar tchar 21560a-4 note : tchar = 10-bit transmission character
am79761 11 preliminary figure 19. receiving two consecutive k28.5 + tcharacter transmission words rclk rclkn com_det rxd[0:9] k28.5 k28.5 tchar tchar tchar tchar potentially corrupted 21560a-5
12 am79761 preliminary absolute maximum ratings storage temperature . . . . . . . . . . . .-65 c to +150 c ambient temperature under bias . .-55 c to +125 c power supply voltage (v dd ) . . . . . . . -0.5 v to +4.0 v dc voltage (pecl inputs) . . . . . .-0.5 v to v dd +0.5 v dc voltage (ttl inputs). . . . . . . . . . . -0.5 v to +5.5 v output current (ttl outputs) . . . . . . . . . . . . - 50 ma output current (pecl outputs) . . . . . . . . . . . - 50 ma maximum input esd (human body model) . . . 1500 v stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges temperature (t a ) 0 c to +70 c for 14 x 14 mm pqfp . . . . . . . . . . . . . 0 c to +50 c for 10 x 10 mm pqfp power supply voltage (d vdd ) . . . . . . . . . +3.3 v 5% operating ranges detne those limits between which functionality of the device is guaranteed. dc characteristics (over recommended operating conditions) symbol parameter description test conditions min typ max unit v ih input high voltage (ttl) 2.0 5.5 v v il input low voltage (ttl) 0 0.8 v i ih input high current (ttl) v in =2.4 v 50 500 m a i il input low current (ttl) v in =0.5 v ? ? -500 m a v oh output high voltage (ttl) i oh = -1.0 ma 2.4 ? ? v v ol output low voltage (ttl) i ol = +1.0 ma ? ? 0.5 v d v out75 tx output differential peak-to- peak voltage swing 75 w to v dd e 2.0 v 1200 ? 2200 mvp-p d v out50 tx output differential peak-to- peak voltage swing 50 w to v dd e 2.0 v 1200 ? 2200 mvp-p d v in receiver differential peak-to- peak input sensitivity rx internally biased to v dd /2 400 ? 3200 mvp-p i dd supply current outputs open, v dd = v dd max ? 210 290 ma p d power dissipation outputs open, v dd = v dd max ? 700 1000 mw
am79761 13 preliminary figure 20. input structures d vdd input current limit r r d vss d vss refclk and ttl inputs a high speed differential input (rx ) b input input all resistors 3.3k d vdd 21560a-6
14 am79761 preliminary key to switching waveforms ac characteristics figure 21. transmit timing waveforms table 21. transmit ac characteristics must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal symbol parameter description test conditions min max unit t 1 txd[0:9] setup time to the rising edge of refclk measured between the valid data level of txd[0:9] to the 1.4 v point of refclk 1.5 ns t 2 txd[0:9] hold time after the rising edge of refclk 1.0 ns t sdr ,t sdf tx rise and fall time 20% to 80%, 75 w load to v ss , tested on a sample basis 300 ps t lat latency from rising edge of refclk to txd0 appearing on tx - bc = bit clocks ns = nano second 11bc - 1ns refclk txd[0:9] 10 bit data data valid data valid data valid t 1 t 2 21560a-7
am79761 15 preliminary ac characteristics (continued) figure 22. receive timing waveform table 22. receive ac characteristics symbol parameter description test conditions min max unit t 1 data or com_det valid prior to rclk/rclkn rise measured between the 1.4 v point of rclk or rclkn and a valid level of rxd[0:9]. all outputs driving 10 pf load. 3.0 ns t 2 data or com_det valid after rclk or rclkn rise 2.0 ns t 3 deviation of rclk rising edge to rclkn rising edge delay from nominal. nominal delay is 10 bit times. tested on sample basis -500 500 ps t 4 deviation of rclk, rclkn frequency from nominal. whether or not locked to serial data -1.0 1.0 % t r , t f rxd[0:9], com_det, rclk, rclkn rise and fall time between v il(max) and v ih(min) , into 10 pf load. 2.4 ns r lat latency from rx to rxd[0:9] bc = bit clock ns = nano second 15 bc + 2 ns 34 bc + 2 ns t lock data acquisition lock time @ 1.25 gbps 8b/10b idle pattern. tested on a sample basis 2.0 m s receive data jitter receive data jitter power dbc, rms for 10 -12 bit error ratio tested on a sample basis ?0ps t 1 t 2 rclk rclkn rxd[0:9] data valid data valid data valid t 3 t 4 21560a-8 delay f baud 10 ----------- t 3 = f rclk f refclk 2 ------------------- -t 4 = phasenoise 100khz 1 2 bittime ------------------------------- -
16 am79761 preliminary reference clock requirements figure 23. refclk timing waveform table 23. reference clock requirements symbol parameter description test conditions min max units fr frequency range range over which both transmit and receive reference clocks on any link may be centered 123 127 mhz fo frequency offset maximum frequency offset between transmit and receive reference clocks on one link -200 200 ppm dc refclk duty cycle measured at 1.5 v 30 70 % t rcr ,t rcf refclk rise and fall time between v il(max) and v ih(min) 1.0 ns refclk t l t h v ih (min) v il (max) 21560a-9
am79761 17 preliminary measurements figure 24. parametric measurement information t r t f v ih(min) v il(max) ttl input and output rise and fall time receiver input eye diagram jitter tolerance task mask serial input rise and fall time 80% t r t f 20% bit time amplitude eye width% 75 w v dd ?2.0 v z 0 = 75w 10 pf parametric test load circuit ttl ac output load serial output load 21560a-10
18 am79761 preliminary measurements (continued) figure 25. transmitter jitter measurement method bert pattern generator clk = 1.25 ghz data = 00000 0000011111 11111 data pat sync am79761 txd[0:9] refclk tx+ tx- digitizing scope trigger 1.25 gbps single-ended measurement 125 mhz 125 mhz trigger data 2 bit time 7 bit time 8 bit time 9 bit time 12 bit time 17 bit time 19 bit time 20 bit time 18 bit time 10 bit time bert pattern generator clk = 1.25 ghz data = 00000 0000011111 11111 data data am79761 txd[0:9] refclk tx+ tx- digitizing scope trigger 1.25 gbps single-ended measurement 125 mhz 125 mhz rj -k28.7 0011111000 random jitter measurement random jitter (rj) measurements performed according to fibre channel 4.3 annex a, test methods, section a.4.4. measure standard deviation of all 50% crossing points. peak to peak rj is 7 sigma of distribution. deterministic jitter measurement deterministic jitter (dj) measurements performed according to fibre channel 4.3 annex a, test methods, section a.4.3. measure time of all the 50% points of all ten transitions. dj is the range of the timing variation from expected. -k28.7 0011111000 dj -k28.5 0011111010 k28.5 1100000101 21560a-11 transmitter output jitter allocation t rj serial data output random jitter (rms) rms, tested on a sample basis (refer to figure 8) ?0ps t dj serial data output deterministic jitter (p-p) peak to peak, tested on a sample basis (refer to figure 8) 100 ps
am79761 19 preliminary thermal considerations the am79761 is packaged in a 14-mm or a 10-mm conventional pqfp with an internal heat spreader. these packages use an industry-standard eiaj footprint, but have been enhanced to improve thermal dissipation. the construction of the packages are as shown in figure 26. figure 26. package cross section table 24. thermal resistance the am79761 is designed to operate with a junction temperature up to 105 o c. the user must guarantee that the temperature speci?ation is not violated. with the thermal resistances shown above, the 10x10 pqfp can operate in still air ambient temperatures of 50 o c, while the 14x14 pqfp can operate in still air am- bient temperatures of 72 o c. if the ambient air tempera- ture exceeds these limits then some form of cooling through a heatsink or an increase in air?w must be provided. notes: 1. 50 o c=110 o c-1w*(10 o c/w+50.8 o c/w) 2. 72 o c=110 o c-1w*(95 o c/w+29 o c/w) symbol description 10 mm value 14 mm value units q jc thermal resistance from junction to case 10.0 9.5 o c/w q ca thermal resistance from case to ambient in still air including conduction through the leads. 50.8 29 o c/w q ca-100 thermal resistance from case to ambient with 100 lfm air?w 41.2 26.1 o c/w q ca-200 thermal resistance from case to ambient with 200 lfm air?w 36.9 23.8 o c/w q ca-400 thermal resistance from case to ambient with 400 lfm air?w 31.8 20.5 o c/w q ca-600 thermal resistance from case to ambient with 600 lfm air?w 27.8 17.9 o c/w copper heat spreader plastic molding compound lead bond wire die 21560a-12
20 am79761 preliminary physical dimensions pdh064 64-pin (measured in millimeters) trademarks copyright ?1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. gigaphy is a trademark of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.

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